Efficient PCB manufacturing depends on early consideration of Design for Testability (DFT) to maximise test effectiveness. This article explores the decisions that should be made early in the design process to prevent testability bottlenecks as these can reduce production capacity and create challenges for test engineers on the production line.

Good Documentation

Development of manufacturing test systems relies on the fundamental design of the PCB, which can be broken down into three key elements:

1. Components – defined by the Bill Of Materials (BOM).

2. Logical interconnections – defined by the schematic and netlist.

3. Physical implementation – defined by the layout.

The schematic is the primary, human-readable design document that is used by both the test developers and the engineers who debug faulty boards. By applying good DFT practices when creating this document, design engineers will accelerate both test development and board debugging. Here are some commonly overlooked best practices for creating well-documented circuits.

1. Netlists – Important details, such as logic voltage level, target device and bus function, can be communicated through well-labelled nets. This helps engineers on the production line to quickly understand a PCB’s function at a glance and isolate a fault’s root cause.

2. Disconnected Pins – Keep all unused and disconnected pins documented within the netlist and as accessible as possible. This helps develop test coverage of these pins for shorts and ‘stuck-at’ faults (where a signal is stuck high or low), and enables defect detection in chips, even if the pins themselves aren’t necessary for the PCB’s current specification.

High Frequency Net Isolation

Test protocols such as JTAG boundary scan testing operate at low frequency. In addition, testing inclusions such as test points and probes can introduce impedance mismatches and discontinuities. This means that keeping high frequency nets functionally isolated can avoid issues of interference introduced by test circuitry.

Power Domain Separation

Keeping power domains well-labelled and functionally separated helps quickly isolate power faults. The current draw of each device on your PCB can be an early indication of faults in joints or chip manufacturing before testing has even begun. Consider integrating power monitors into key power domains on your board to capitalise on this.

Reliable Clock Signals

Components on a PCB typically depend on clock signals generated by other components. Using dedicated oscillators instead of programmable devices helps avoid issues. Since programmable devices are often disabled or blanked during testing, this dependency can make faults difficult to isolate and identify. It can also be problematic because test software usually operates at much lower frequencies than those required to drive correct clock signals for ICs.

Reset Circuitry

Reset circuitry is essential for isolating faults. It ensures functional blocks can be reset, disabled, and placed into test or debug modes. While often not needed in typical use, reset circuitry is essential during manufacturing for the safe and effective testing of programmable components like Memory, FPGAs and PLDs. Consider implementing a sure way to disable these components, creating high impedance states to signal lines to avoid issues like Back Powering.

Loopbacks

Test coverage of certain circuit areas, particularly analogue sections, can often only be achieved through loopbacks or external test fixtures. These areas should be kept functionally separated and accessible through the use of test headers. Using loopback tests can simplify test fixture development by providing a cheaper and more convenient alternative, however this must be planned early in the development process. This can be achieved by designing the circuit to allow analogue signals to be redirected back for functional testing, for example through an on-board Analogue to Digital Converter (ADC).

JTAG Chaining

JTAG chaining decisions directly impact test time, fault isolation, and system reliability. If multiple JTAG enabled devices appear in your circuit, it must be decided early on whether they should be chained together. An in-depth discussion of factors that you might want to consider while making this decision can be found here. Unique chains for each JTAG-enabled device ensure functional partitioning of the circuit, reduce debug time and speed up test execution. In the situation where JTAG devices must be chained together, we recommend placing headers to allow fitting jumpers to connect the TDI and TDO nets of each JTAG device in the chain, and also disconnect their TDO pin. This allows devices to be manually removed from the chain with ease, perhaps because one device is found to be completely non-functional.

1. Pin coverage – boundary scan testing relies on I/O cells placed around the periphery of the chip. Manufacturers may decide not to place these cells on certain pins on their chip, as they can impede high frequency nets or damage sensitive nets if driven inappropriately. These ‘linkage’ pins are inaccessible during boundary scan testing. Always review pin coverage when selecting components.

2. BSDL Support – Boundary scan test systems like XJTAG depend on a description of how the device implements boundary scan in the form of a Boundary Scan Description Language (BSDL) file. Every JTAG compliant device will have one, but they may not always be readily available from manufacturers. Acquiring the correct BSDL file during the design stage can accelerate test development and helps to confirm the JTAG capabilities of your selected device, and alert you to the device’s operational requirements through its listed ‘compliance’ pins.

Accessible Industry Standard Ports

Where possible, easy access to the TDI, TDO, TCK, TMS and any associated reset pins should be incorporated. It is important to consider which connection accessories you will use early, as although this port may never see use after the manufacturing stage, it is crucial to isolating faults on the production line.

Beyond this, a common mistake is failing to consider signal integrity. Guides on ensuring proper grounding and termination can be found at these links.

We would recommend using 20-way connectors with a signal integrity 10 pinout to easily insert tap signals into your layout, with the necessary signal integrity features built in.

Where there are no JTAG enabled devices in a circuit, it is beneficial to include standard headers on the signals for other common industry standard methods of communication with on-board devices, such as I² C and SPI. Another common approach to in circuit tests is a ‘bed of nails’ approach, where connections to the circuit are made through laying the Unit Under Test (UUT) across an array of vertical pins. If designing for this approach, it is important to consider laying out standardised, accessible test points to cover all nets inaccessible through headers and device pins. Consider that some devices may have pins with too fine of a pitch to be accessed via probe, and BGA pinned chips can’t be probed directly. Ensure that these test points are given good clearance from other components and any high-speed nets that they could impede, with diameters wider than the precision of the probing fixture for reliable connections.

Note that these choices apply regardless of your testing method, as test points are useful for helping test engineers precisely identify detected faults.

Conclusion

By addressing testability early in the design process, you can significantly reduce development time, improve fault coverage, and avoid costly production delays. To further streamline your test development, don’t hesitate to contact XJTAG for expert advice on how XJTAG tools can accelerate prototyping and ensure manufacturing reliability.

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