I/O, Let’s Go! What exactly are I/O cells?

Welcome reader!

Digital integrated circuits (ICs) use input/output (I/O) cells to connect their internal logic to the outside world – all signals that leave or enter the IC will pass through an I/O cell. These cells are placed along the periphery of the chip and are designed to handle a diverse range of requirements including electrical compatibility, signal integrity, timing, and anything else that’s needed between the internal logic and the external pin.

These factors can include providing protection against electrostatic discharge (ESD), controlling impedance, and level-shifting the voltage on the pin. These I/O cells can be configured as an input, output, or both input and output (bidirectional), and some also have specialised functions depending on their application.

Basic FPGA I/O Cell

This example, Figure 1, considers a simple bidirectional I/O cell in a field programmable gate array (FPGA).

This example bidirectional cell possesses the following characteristics:

• Input/Output buffers to receive/transmit signals from/to the pad (external pin).

• Control signals from the write/read logic to tristate the output/input buffer.

• ESD protection, in this example via the two diodes. In normal operation (reverse-biased), no current flows through either diode, but during a large enough voltage spike (V_DD + Diode Threshold, or V_SS - Diode Threshold) current will be shunted from the pad to either the supply or ground, depending on the polarity of the spike, protecting the internal circuit.

Brief Boundary Scan Overview

There is a more verbose explanation of boundary scan on the XJTAG website, but as a brief overview, the relevant IEEE standard (1149.1, JTAG), provides methodology to test interconnects on printed circuit boards (PCBs) and within ICs without requiring physical access to the pins. This is achieved by using some more silicon at the periphery or the ’boundary’ of the IC, on each of the I/O cells the IC designer chooses. This extra silicon is referred to as ’JTAG Cells’ or ’Boundary Scan Cells’.

XJTAG can use its access to these JTAG cells to set their state or read input signals from them, performing both interconnection tests between JTAG devices and functionality-based testing on non-JTAG devices in a circuit. This can be achieved with no firmware or images required on the devices.

Boundary Scan I/O Cells

Boundary Scan Cells in your ICs!

Boundary Scan Cells are added to the I/O cells between the pads of the device and the buffers to the internal logic in an IC. The JTAG TAP (Test Access Port) has a data in pin (TDI) which is connected to the first boundary scan cell. Each boundary scan cell is connected to the next one, until the signal gets to the final cell which connects to the data out pin (TDO) of the TAP. This forms a ’scan chain’ which acts like a shift register from TDI to TDO with all the Boundary Scan Cells in-between and can be extended across multiple devices by connecting one device’s TDO pin to the next device’s TDI.

Boundary Scan cells are standardised configurations of several logic devices that can be connected and used for different functions in a scan chain. Multiple Boundary Scan Cells can be assigned to the same pad to achieve a particular function.

Moving round the JTAG State Machine, the chain can be put into different modes so that the Boundary Scan Cells:

• ’Capture’ the data from the pads.

• ’Shift’ the data through the chain.

• ’Update’ the driving values on the pads.

Using these three instructions, test data can be serially loaded in to and out of the device, enabling testing on any Boundary Scan enabled pin without needing direct access.

This example in Figure 3 considers a simple bidirectional I/O cell in an FPGA that has JTAG Boundary Scan implemented.

Common issues during test: false positives often arise due to internal logic programming and I/O cell configuration. When the logic in an FPGA is programmed, it can affect the device beyond the internal logic, connecting or disconnecting pull resistors and changing the pin’s behaviour. This can lead to unexpected results during testing and cause tests to fail when there’s no problem.

Additionally, some ICs require specific I/O cell configurations to power the Boundary Scan Cells — details that are often poorly documented. For instance, most devices’ Boundary Scan Cells will use the voltage domain assigned to their respective I/O bank and certain devices mandate configuration (e.g. configure differential FPGA pins to be differential in an image) before Boundary Scan Cells operate per the JTAG standard.

It is recommended, unless specified otherwise in documentation, to always have a fully erased/blank JTAG device for testing.

The types of Boundary Scan Cells

The first JTAG standard 1149.1 (1990) introduced Boundary Scan Cell types for pins that operate with DC signals, while 1149.6 (2003) extended and modified these cells for AC operation such as differential pairs and AC-coupling. It is up to the IC designer to select and connect appropriate cell-types for the function of the pin in the device.

Boundary Scan Cells are assigned functions describing the purpose they serve in the scan chain. Different cell types can be configured for different functions, with some overlap, and have their own characteristics. Before we look at the types of Boundary Scan Cells, let’s review what functions we can assign to them:

• INTERNAL - Internal cell, not associated with a system pin.

• OBSERVE ONLY - Observe-only cell, associated with a system pin.

• CLOCK - Observe-only cell for clock pins (supports INTEST instruction)

• INPUT - Control-and-observe input cell

• OUTPUT2 - 2-state (1, 0,) output cell

• OUTPUT3 - 3-state (1, 0, Hi-Z) output cell

• CONTROL - Output enable or direction control cell

• CONTROLR - CONTROL with pre-set/clear at Test-Logic-Reset

• BIDIR - Cell on a bidirectional pin acting as either an output or an input. Below shows a table on what functions can be assigned to each Boundary Scan Cell type:

Table 1: Boundary Scan Cell Types and their Assignable Functions

Some Boundary Scan Cells replace the BC prefix with AC to show that they are 1149.6 compliant cells. Additionally, some silicon vendors have defined custom cell types that don’t strictly follow the standard. One common example of this is the LV prefix, used to designate LVDS (Low Voltage Differential Signalling) compatible pins.

Journey to the centre of a Boundary Scan Cell

Now that the basics of Boundary Scan Cells have been covered, let’s consider a real compliant example from the JTAG standard, using ’BC_2’ and ’BC_7’ cells working together to add boundary scan to a single pin.

In Figure 4, each cell is encapsulated by a dashed line; the top cell is a ’BC_2’ cell and the bottom one is a ’BC_7’ cell. The ’BC_7’ cell observes the output/input data and drives the D-Type flip-flop that outputs onto the external pin. The ’BC_2’ cell controls the output enable of the output flip-flop. The 2:1 multiplexers are controlled by various ’Mode’ signals. Depending on the currently loaded JTAG instruction, e.g. ’EXTEST’ or ’SAMPLE’, appropriate values will be set on each ’Mode’ signal. The expected values per instruction are defined in the standard.

Conclusions

In short, boundary scan enabled devices have some extra logic between the functional circuitry of the device and the pins that connect to the rest of the circuit. With this extra logic, a JTAG controller can read or set values on many of the pins, although the exact capabilities vary between different pins and different devices. This extra control allows systems such as XJTAG to apply specific signals to the circuit, giving you the capacity to test and debug boards, program devices and trial parts of the board, even if the code hasn’t been written for them yet.

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