The Evolution of PCB testing

Welcome reader!

The first printed circuit board (while quite different from today’s designs) is attributed to Paul Eisler in 1936, however it wasn’t until 1943 that PCBs began to be manufactured at scale, driven by demand from the U.S. military. Even from the earliest stages, fault detection and testability were essential considerations. Visual inspection, often with magnifiers, was initially used to verify solder joints.

Bed-of-nails testing

By the 1960s, PCBA manufacturing processes had become semi-automatic, but test automation lagged until the 1970s when Bed-of-Nails (BoN) testing became popular, significantly improving both test speed and accuracy. BoN testing is an in-circuit testing (ICT) process that involves creating a custom fixture equipped with spring-loaded pins that contact designated test points on the PCB. Testing with a BoN typically includes two phases: power-off and power-on testing. Power-off tests validate physical connectivity and perform open/short detection via impedance measurements, then the power-on tests actively stimulate components to confirm their presence, orientation, and electrical bonding. In the 1970s, a typical test cycle took between 30 seconds and 3 minutes. Today, optimised BoN systems can perform tests in as little as 7 seconds.

BoN testing requires direct physical access to the board. As designs evolved, particularly with the shift from through-hole to surface-mount technology and double-sided assemblies, test point access declined. Tighter component pitches and denser layouts have made it increasingly challenging to physically align the test pins on the BoN with the test points on the PCB. Furthermore, the time and cost required to build a custom fixture for each board design is disadvantageous.

Flying probe testing

Flying probe testing (FPT), developed in the 1980s, offers a more flexible alternative. This approach retains the principle of physical contact but replaces the custom fixture with movable probes, allowing board designs to be tested without the need for a custom fixture. Flying probe testing is, however, significantly slower than BoN; testing a board typically takes between 10 minutes and an hour with today’s tools, depending on board and test complexity.

Automated X-ray inspection

Next came automated X-ray inspection (AXI), introduced to solve the problem of components with inaccessible pins, such as BGAs. The penetration power of X-rays enables AXI to inspect internal solder joints and hidden features without needing physical contact. While this method effectively addresses access issues, especially in high-density boards, 3D X-ray testing can take hours per board, and system costs are high, limiting its use to specific high-value applications.

These limitations drove the formation of the Joint European Test Action Group (JETAG), which eventually included North American participants and became known simply as JTAG. The solution proposed by the group was a shift register implemented around the boundary of integrated circuits – a system they called boundary scan.

Boundary scan testing

In 1990, the IEEE 1149.1 standard formally defined the approach, specifying the four signal lines (TDI, TDO, TMS, and TCK – data in, data out, mode select and clock) and the behaviour of the Test Access Port (TAP) controller. Boundary scan allows test data to be shifted into and out of a device, enabling test software to stimulate and observe circuit behaviour without requiring physical access to component leads. By cycling through various signal combinations on the pins, the system can detect shorts, opens, and stuck-at faults across accessible nets.

One of the key benefits of boundary scan is that, since it eliminates the need for physical probing, test points can be removed – it only requires the four TAP signals to be available on a connector. Additionally, the tests are swift, typically taking around a minute for interconnect tests and functional tests of some devices.  Multiple JTAG devices can be daisy-chained, allowing them to share a single set of TAP connections or they can be placed on separate scan chains for increased speed. With these methods, access can be gained to all JTAG devices, maximising test coverage on the board.

XJTAG’s suite of tools provides a comprehensive system to setup and execute boundary scan testing:

• XJDeveloper guides users through board setup, provides statistics on test coverage, and supports functional testing of components like LPDDR, eMMC, and flash memory.

• XJRunner enables tests created in XJDeveloper to be run in production environments without exposing editable project files, preserving design IP.

• XJAnalyser allows live control and observation of individual JTAG pins, helping engineers quickly confirm fault locations.

Boundary scan continues to evolve. Standards such as IEEE 1149.6 extend testing capabilities to high-speed differential and AC-coupled signals, another area supported by XJTAG’s platform. Additionally, as JTAG adoption grows in sectors such as aerospace, automotive, and communications, the complexity and number of JTAG-enabled devices on boards are increasing. XJTAG has responded with tools like the XJLink-PF40, which supports up to 8 simultaneous JTAG chains in four voltage domains, offering scalable performance for larger designs.

JTAG was developed to solve a real engineering problem: how to reliably test modern, complex PCBs without relying on physical access. Since its standardisation, it has become a foundational tool in the electronics manufacturing and validation process. XJTAG gives you the tools you need to use the built-in capabilities in your devices to maximise your test coverage.

If you would like more information on XJTAG or would like to sign up for a free trial, please get in contact with us here: XJTAG.com/contact

Enjoyed this update? Please forward to a colleague who may find it interesting.