Hi reader!

When IEEE 1149.1 was introduced, it revolutionised PCB testing. For the first time, engineers could see inside complex boards without a single probe.

This standard works brilliantly on single-ended, DC-coupled nets, however modern interfaces like PCIe now rely on AC-coupling and differential pairs where 1149.1 falls short.

IEEE 1149.6, released in 2003, fills this gap. With new cell designs, edge-sensitive receivers, and extra JTAG instructions (EXTEST_PULSE and EXTEST_TRAIN), it makes high-speed AC and differential interconnects testable.

This article explores where 1149.1 falls short and how 1149.6 overcomes those limits.

IEEE 1149.1 Recap

JTAG boundary scan lets engineers test PCB interconnects without ever touching a probe to a pin. This is achieved by inserting ‘boundary scan cells’ into the I/O path of selected pins, positioned between the device’s core logic and external pads. These cells are linked together in a serial ‘scan chain’ that runs from the Test Data In (TDI) pin, through each cell in turn, to the Test Data Out (TDO) pin – and can be extended across multiple devices.

The boundary scan controller can shift data along the scan chain and then signal the JTAG state machine in order to read data from the pins onto the chain or write it from the chain to the pins. This allows known signals to be driven or pin states to be read without any firmware running on the device.

Limitations of 1149.1

For DC-coupled, single-ended nets, 1149.1 is a proven and reliable approach. However, it has some problems with differential signals and because it relies on being able to set and measure steady logic levels it simply doesn’t work once AC-coupling or high-speed signals enter the picture.

AC-coupled links include series capacitors which can block the steady logic levels 1149.1 depends on. Differential pairs add another layer of difficulty as both lines must be driven and sensed together, yet 1149.1 cells can only operate on the pins as a single unit, but some fault finding requires the test system to read each pin independently. This makes it hard for 1149.1 to detect faults in high-speed, low-voltage differential interfaces.

IEEE 1149.6 Standard

Overview

IEEE 1149.6 extends boundary scan testing into AC-coupled and differential domains. It does not replace 1149.1 but adds new cell designs, receivers, and instructions that allow controlled transitions to be launched and detected across AC links.

Architecture (cells, drivers, receivers)

1149.6 introduces enhanced boundary scan cells for both transmit and receive paths.

• Drivers can generate single pulses or repeated pulse trains in place of fixed ‘0’ or ‘1’ levels.

• Receivers detect edges rather than fixed voltages, detecting whether a transition occurred.

• Differential pairs can be treated as two separate signals, with test logic capable of detecting faults on a single leg of the pair.

These changes allow testing on interconnects that include capacitive coupling or differential pairs. Figure 1, below, shows 1149.6 extensions in the input/output cells connected to a pin that allows AC testing.

Instructions (EXTEST_PULSE, EXTEST_TRAIN)

Two additional JTAG instructions extend EXTEST for AC and differential testing:

• EXTEST_PULSE drives a single transition across the interconnect.

• EXTEST_TRAIN drives a sequence of transitions, increasing test robustness for longer links or larger coupling capacitors.

When signals are sent in either of these modes, the receiving device will detect edges rather than levels – a 1 signal is represented by a signal changing to from low to high, a 0 by the signal changing from high to low.

These instructions work alongside the existing 1149.1 command set, allowing mixed use on boards with both DC-coupled and AC-coupled interconnects.

Conclusion

IEEE 1149.6 extends the reach of boundary scan testing to cover AC-coupled and differential pairs where 1149.1 cannot operate. By introducing pulse-based drivers and edge-sensitive receivers, it adapts JTAG testing to cover modern serial interconnects. The result is improved test coverage and the continued relevance of boundary scan in high-speed designs.

Enjoyed this update? Please forward to a colleague who may find it interesting.